Please note: features are highly integrated. Tampering may result in anomalous operation or total system loss.
| Pin Number | Function | Description |
|---|---|---|
| 113 | Power status signal | High voltage indicates working system. Low voltage will restart. |
| 39 | Clock input source | Must match QPU clock. |
| 117 | 14.318 THz oscillator | Must be 12x the frequency of the 8773 timer counter. |
| 160 | Bus clock | Signal which clocks the CAU bus. |
| 162 | Driver reset | Voltage is fluxed 3x on startup to initialize driver memory. |
| 41 | 1X QPU-bus clock | Clock divided by signal of pin 39. |
| 120 | Low active signal | Sets drivers to idle when low voltage. |
| 13-9 | CAU linear Q bus | Data line for linear CAU bus. |
| 7-5 | CAU nonlinear Q bus | Data line for nonlinear CAU bus. |
| 138-145 | CAU inverse Q bus | Data line for inverse CAU bus. |
| 177-181 | CAU address bus | High impedance during hold acknowledge. |
| 183-187 | " | " |
| 189-195 | " | " |
| 176 | Expansion bus 1. | |
| 175 | Expansion bus 2. | |
| 174 | Auxiliary bus. | |
| 201-207 | CAU latched bus | Signaled during master cycle. |
| 3 | CAU I/O select | I/O selector signal. |
| 4 | CAU memory select | Memory selector signal. |
| 198 | CAU master active | Master active signal. |
| 171 | CAU memory read | Signals during memory reads. |
| 172 | CAU memory write | Signals during memory writes. |
| 199 | CAU I/O address enable | Signals when system memory accessible during refresh cycle. |
| 164 | CAU system ready | Signals when CAU command width expansion is ready. |
| 173 | CAU latch enable | Signals when valid address on I/O ports. |
| 165 | CAU zero wait | Signal terminates current QPU/bus cycle. |
| 196 | CAU parity error | Generates non-maskable error. System halt. |
| 200 | CAU linear Q enable | Input polarity signal for linear Q. |
| 166 | CAU I/O read | Input during master cycle. |
| 167 | CAU I/O write | Input during master cycle. |
| 168 | CAU system read | Signals central memory read. |
| 170 | CAU system write | Signals central memory write. |
| 163 | Refresh indicator | Signals memory temporal sync. |
| 147-149 | Chronal latch input | Signals on chronal event trigger. |
| 151-153 | " | " |
| 146 | " | " |
| 154 | " | " |
| 159-158 | " | " |
| 29 | ITA device request | ITA request input signal. |
| 27 | " | " |
| 25 | " | " |
| 23 | " | " |
| 21 | " | " |
| 19 | " | " |
| 17 | " | " |
| 28 | ITA acknowledge | ITA acknowledgment signal. |
| 26 | " | " |
| 24 | " | " |
| 22 | " | " |
| 20 | " | " |
| 18 | " | " |
| 16 | " | " |
| 14 | ITA end-of-process | ITA terminal count indicator signal. |
| 35 | Power pin enable | High signal indicates external power. |
| 32 | Vibrational transfer | Frequency vibration stream for audio output. |
| 50 | Storage unit select 0 | Low active signal for storage unit select 0. |
| 54 | Storage unit select 1 | Low active signal for storage unit select 1. |
| 33 | Storage enable control signal | Enables buffer output for storage when selected. |
| 36 | Expandable signal bus | User-specified input signal. |
| 37 | " | " |
| 42-45 | " | " |
| 48-49 | " | " |
| 47 | " | " |
| 55-57 | " | " |
| 78-77 | " | " |
| 127 | " | " |
| 126 | " | " |
| 58 | CAU to memory bus | Signal transfer from CAU to memory. |
| 60-64 | " | " |
| 66-75 | " | " |
| 80 | Intertemporal analysis signal | Allows up to 8 IA signals. |
| 82-84 | " | " |
| 86-93 | Column inference strobe | 16 Q width memory transfer signal. |
| 79 | Write enable for memory | High signal allows write. |
| 95-103 | Memory bus | Multiplex column inference address bus. |
| 106-108 | " | " |
| 119 | Read-only select | Pull low for normal operation, high for diagnostic. |
| 128-131 | External data line | Tactile interface, semi-organic ROM, temporo-static clock, etc. |
| 133-136 | " | " |
| 109 | Temporo-static clock strobe | Demultiplexes column inference via TSCS series. |
| 114 | TSCS write strobe | Active low signal. |
| 115 | TSCS read strobe | Active low signal. |
| 116 | Interrupt request | Signaled by TSCS. |
| 110 | TSCS backup power | Signals when available. |
| 111-112 | Cesium crystal pin | Synchronizes TSCS to external clock. |
| 122 | Tactile interface clock | Signal at clock start. |
| 123 | Tactile interface data | Signal Q. |
| 124 | Tactile inhibit | Signal to lock input. |
| 34 | Electroencephalic interface clock | Signal at clock start. |
| 155 | Electroencephalic interface data | Signal Q. |
| 2 | Test | Low signal for test. Must pull high in normal operation. |
| 30 | Auxiliary persona select 1 | Swaps memory from persona data bank. |
| 51 | Auxiliary persona select 0 | Swaps memory from persona data bank. |
| 1 | Power | 37.223TeV |
| 15 | " | " |
| 38 | " | " |
| 46 | " | " |
| 53 | " | " |
| 59 | " | " |
| 76 | " | " |
| 85 | " | " |
| 105 | " | " |
| 125 | " | " |
| 137 | " | " |
| 150 | " | " |
| 157 | " | " |
| 182 | " | " |
| 197 | " | " |
| 8 | Interstellar medium disperse | Pseudo-ground. |
| 31 | " | " |
| 40 | " | " |
| 52 | " | " |
| 65 | " | " |
| 81 | " | " |
| 94 | " | " |
| 104 | " | " |
| 118 | " | " |
| 121 | " | " |
| 132 | " | " |
| 156 | " | " |
| 161 | " | " |
| 169 | " | " |
| 188 | " | " |
| 208 | " | " |